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atmel-5227f-seeprom-at24hc04b-datasheet_022014 features ? write protect pin for hardware data protection ? utilizes different array protection compared to the at24c04b ? low-voltage and standard-voltage operation ? 1.8v (v cc = 1.8v to 5.5v) ? internally organized 512 x 8 (4k) ? 2-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 1mhz (5v) and 400khz (1.8v, 2.5v, 2.7v) clock rate ? 16-byte page ? partial page writes allowed ? self-timed write cycle (5ms max) ? high reliability ? endurance: 1,000,000 write cycles ? data retention: 100 years ? 8-lead pdip, 8-lead jedec soic, and 8-lead tssop packages ? die sales: wafer form, tape and reel, and bumped wafers description the at24hc04b provides 4096 bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 512 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at24hc04b is available in space-saving 8-lead pdip, 8-lead jedec soic, and 8-lead tssop packages and is accessed via a 2-wire serial interface. in addition, the entire family is available in 1.8v (1.8v to 5.5v) version. at24hc04b i 2 c-compatible (2-wire) serial eeprom 4k (512 x 8) datasheet
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 2 1. pin configurations and pinouts table 1-1. pin configuration 2. absolute maximum ratings* pin name function nc no connect a1 and a2 address inputs sda serial data scl serial clock input wp write protect v cc device power supply 1 2 3 4 8 7 6 5 nc a1 a2 gnd v cc wp scl sda 8-lead pdip note: drawings are not to scale. top view top view top view 8-lead tssop 1 2 3 4 8 7 6 5 nc a1 a2 gnd v cc wp scl sda 8-lead soic nc a1 a2 gnd v cc wp scl sda 1 2 3 4 8 7 6 5 operating temperature ??????????????????????? ? 40 ? c to +125 ? c storage temperature ??????????????????????????? ? 65 ? c to +150 ? c voltage on any pin with respect to ground ???????????????????????????? 1.0v to +7.0v maximum operating voltage . . . . . . . . . . . . . . . 6.25v dc output current . . . . . . . . . . . . . . . . . . . . . . 5.0 ma *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 3. block diagram figure 3-1. block diagram 4. pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, and a0): the a2 and a1 pins are device address inputs that must be hardwired for the at24hc04b. as many as four 4k devices may be addressed on a single bus system. the a0 pin is a no connect. (device addressing and page addressing are discussed in detail in section 7., ?device addressing and page addressing? ). write protect (wp): the at24hc04b has a wp pin which provides hardware data protection. the wp pin allows normal read/write operations when connected to ground (gnd). when the wp pin is connected to v cc , the write protection feature is enabled and operates as shown. table 4-1. write protect start stop logic vcc gnd wp scl sda a 2 a 1 a 0 serial control logic en h.v. pump/timing eeprom data recovery serial mux x dec d out /ack logic comp load inc data word addr/counter y dec r/w d out d in load device address comparator wp pin status part of the array protected at v cc upper half (2k) array at gnd normal read/write operations
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 4 5. memory organization at24hc04b, 4k serial eeprom: the 4k is internally organized with 32 pages of 16 bytes each. random word addressing requires an 9-bit data word address. 5.1 pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. 5.2 dc characteristics note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t ai = 25 ? c, f = 1.0mhz, v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , and scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = -40 ? c to +85 ? c, v cc = +1.8v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.80 5.50 v v cc2 supply voltage 2.50 5.50 v v cc3 supply voltage 2.70 5.50 v v cc4 supply voltage 4.50 5.50 v i cc supply current v cc = 5.0v read at 100khz 0.40 1 ma i cc supply current v cc = 5.0v write at 100khz 2 3 ma i sb1 standby current v cc = 1.8v v in = v cc or v ss 0.60 3 a i sb2 standby current v cc = 2.5v v in = v cc or v ss 1.40 4 a i sb3 standby current v cc = 2.7v v in = v cc or v ss 1.60 4 a i sb4 standby current v cc = 5.0v v in = v cc or v ss 8 18 a i li input leakage current v in = v cc or v ss 0.10 3 a i lo output leakage current v out = v cc or v ss 0.05 3 a v il input low level (1) ? 0.60 v cc x 0.30 v v ih input high level (1) v cc x 0.70 v cc + 0.50 v v ol2 output low level v cc = 3.0v i ol = 2.10ma 0.40 v v ol1 output low level v cc = 1.8v i ol = 0.15ma 0.20 v
5 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 table 5-1. ac characteristics notes: 1. this parameter is ensured by characterization only. 2. ac measurement conditions: ? rl (connects to v cc ): 1.3k ? (2.5v, 5.5v), 10k ? (1.7v) ? input pulse voltages: 0.3v cc to 0.7v cc ? input rise and fall times: ? 50ns ? input and output timing reference voltages: 0.5 x v cc applicable over recommended operating range from t ai = ?40 ? c to +85 ? c, v cc = +5.5v, cl = 1 ttl gate and 100pf (unless otherwise noted). test conditions are listed in note 2 . 1.8v, 2.5v, 2.7v 5v symbol parameter min max min max units f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.20 0.40 s t high clock pulse width high 0.60 0.40 s t i noise suppression time 50 40 ns t aa clock low to data out valid 0.10 0.90 0.05 0.55 s t buf time the bus must be free before a new transmission can start. 1.20 0.50 s t hd.sta start hold time 0.60 0.25 s t su.sta start setup time 0.60 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.30 0.30 s t f inputs fall time (1) 300 100 ns t su.sto stop setup time 0.60 .25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 5.0v, 25 ? c, byte mode 1,000,000 write cycles
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 6 6. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6-1 ). data changes during scl high periods will indicate a start or stop condition as defined below. figure 6-1. data validity start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command (see figure 6-2 ). figure 6-2. start and stop definition stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop condition will place the eeprom in a standby power mode (see figure 6-2 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. . the eeprom sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at24hc04b features a low-power standby mode that is enabled: ? upon power-up. ? after the receipt of the stop bit, and the completion of any internal operations. sda scl data stable data stable data change sda scl start stop
7 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 2-wire software reset: after an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: 1. create a start bit condition, 2. clock nine cycles, 3. create another start bit followed by stop bit condition as shown below. the device is ready for next communication after above steps have been completed. figure 6-3. software reset figure 6-4. bus timing scl 9 start condition start condition stop condition 8 3 2 1 sda dummy clock cycles scl sda in sda out t f t high t low t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 8 figure 6-5. write cycle timing note: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 6-6. output acknowledge t wr (1) stop condition start condition wordn ack 8 th bit scl sda scl data in data out start acknowledge 9 8 1
9 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 7. device addressing and page addressing the 4k eeprom device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in figure 7-1 . figure 7-1. device address the device address word consists of a mandatory ?1?, ?0? sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the next two bits are the a2 and a1 device address bits for the 4k eeprom. these two bits must compare to their corresponding hardwired input pins. the a0 pin is a no connect. the next bit is the memory page address bit. this bit is the msb of the 9-bit data word address. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the chip will return to a standby state. 8. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgement. upon receipt of this address, the eeprom will again respond with a zero, and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time, the eeprom enters an internally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle, and the eeprom will not respond until the write is complete, see figure 8-1 . figure 8-1. byte write 4k 1 0 1 0 a2 a1 p0 r/w msb lsb s t a r t m s b m s b l s b s t o p w r i t e sda line device address word address data l s b a c k a c k a c k r / w
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 10 page write: the 4k eeprom is capable of a 16-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition. figure 8-2. page write the data word address lower four bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than sixteen data words are transmitted to the eeprom, the data word address will roll-over and previous data will be overwritten. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0? allowing the read or write sequence to continue. 9. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: ? current address read ? random address read ? sequential read current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll-over during read is from the last byte of the last memory page to the first byte of the first page. the address roll-over during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition, see figure 9-1 . figure 9-1. current address read s t a r t m s b s t o p w r i t e sda line device address word address (n) data (n) data (n + 1) data (n + x) l s b a c k a c k a c k a c k a c k r / w s t a r t r e a d m s b s t o p sda line device address data l s b a c k n o a c k r / w
11 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 random read: a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition, see figure 9-2 . figure 9-2. random read sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll-over and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition, see figure 9-3 . figure 9-3. sequential read s t a r t s t a r t m s b s t o p w r i t e r e a d sda line device address dummy write word address n device address data n l s b a c k a c k a c k n o a c k r / w m s b l s b m s b l s b sda line r e a d s t o p device address data (n) data (n + 1) data (n + 2) data (n + x) a c k a c k a c k a c k n o a c k r / w
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 12 10. ordering code information notes: 1. b = bulk 2. t = tape and reel ? soic = 4k per reel ? tssop = 5k per reel 3. available in tape and reel and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact the atmel sales office. ordering code lead finish package voltage operation range at24hc04b-pu bulk form only (lead-free/halogen-free) 8p3 1.8v industrial temperature ( ? 40 ? c to 85 ? c) at24hc04bn-sh-b (1) nipdau (lead-free/halogen-free) 8s1 at24hc04bn-sh-t (2) at24hc04b-th-b (1) 8x at24hc04b-th-t (2) at24hc04b-w-11 (3) ? die sale package type 8p3 8-pin, 0.30? wide, plastic dual inline (pdip) 8s1 8-lead, 0.15? wide, plastic gull wing small outline (jedec soic) 8x 8-lead, 4.40mm body, plastic thin shrink small outline (tssop)
13 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 11. part marking scheme drawing no. rev. title 24hc04bsm a 1/16/14 24hc04bsm , at24hc04b package marking information package mark contact: dl-cso-assy_eng@atmel.com aaaaaaaa ###% @ atmlhyww 8-lead soic 8-lead tssop aaaaaaa ###% @ athyww note 2: package drawings are not to scale note 1: designates pin 1 at24hc04b: package marking information catalog number truncation at24hc04b truncation code ###: h4b date codes voltages y = year m = month ww = work week of assembly % = minimum voltage 4: 2014 8: 2018 a: january 02: week 2 l: 1.8v min 5: 2015 9: 2019 b: february 04: week 4 6: 2016 0: 2020 ... ... 7: 2017 1: 2021 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number h: industrial/nipdau u: industrial/matte tin/snagcu trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel aaaaaaaa ###m @ atmluyww 8-lead pdip
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 14 12. packaging information 12.1 8p3 ? 8-lead pdip drawing no. rev. title gpc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view package drawing contact: packagedrawings@atmel.com 8p3 d 06/21/11 8p3, 8-lead, 0.300? wide body, plastic dual in-line package (pdip) ptc
15 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 12.2 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 16 12.3 8x ? 8-lead tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. package drawing contact: packagedrawings@atmel.com h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
17 at24hc04b [datasheet] atmel-5227f-seeprom-at24hc04b-datasheet_022014 13. revision history doc. rev. date comments 5227f 02/2014 update atmel template (no changes to functional specfication). logos, and disclaimer page, part markings to a single page, and package drawings 8p3, 8s1, and 8a2 to 8x. update the random read figure and add the ac measurement conditions note to the ac characteristics table. 5227e 11/2008 update pin configurations. 5227d 01/2008 remove ?preliminary? status. 5227c 08/2007 adde part marking scheme. 5227b 08/2007 update to new template and common figures. adde part marking tables. 5227a 04/2007 initial document release.
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